对大容量的高速低功耗嵌入式存储器的需求不断增加。通常有两种存储器,一个是嵌入式的静态随机存储器(SRAM),另一个是嵌入式动态随机存储器(DRAM)。SRAM有着很高的运行速度,但是SRAM的存储单元是由六个晶体管组成的,在大规模集成电路中SRAM存储阵列将会占据很大的面积。此外SRAM存储单元中晶体管需要相互匹配,这样就会...
通常有两种存储器,一个是嵌入式的静态随机存储器(SRAM),另一个是嵌入式动态随机存储器(DRAM)。SRAM有着很高的运行速度,但是SRAM的存储单元是由六个晶体管组成的,在大规模集成电路中SRAM存储阵列将会占据很大的面积。此外SRAM存储单元中晶体管需要相互匹配,这样就会导致SRAM很难按比例缩小。由一个晶体管和一个电容组...
The simplicity of the cell structure also makes it extremely scalable and cost effective. The challenges of using this cell to satisfy the requirement of embedded SRAM are high-frequency operation, short latency, transparent refresh and soft-error rate. The use of multi-bank architecture and the ...
It uses a single transistor (1T), unlike traditional 1T1C DRAM, or six transistor 6T-SRAM memory cell.Singh, A.Ciraula, M... A Singh,M Ciraula,D Weiss,... - Solid-state Circuits Conference-digest of Technical Papers 被引量: 74发表: 2009年 A systematic study of the sharp-switching...
A deep-trench 1T-SRAM memory cell is disclosed. The deep-trench 1T-SRAM memory cell includes a first conductivity type semiconductor substrate with a main surface. A second conductivity type ion implantation well with a well junction depth is located on the main surface. A gate dielectric layer...
1T1CSRAM It is how memory and circuit to achieve full compatibility static memory with (SRAM), which provides an interface high-density dynamic memory, such as memory cell (one capacitor and one transistor) 1T1C and (DRAM). This circuit is to ove... ソーン,ジェオング-ダック 被引量...
About 1T-SRAM Available in densities up to 128Mbits, MoSys' patented 1T-SRAM technology uses a single transistor cell to achieve its exceptional density while maintaining the refresh-free interface and low latency random memory access cycle time associated with traditional six-transistor SRAM cells...
晟矽微推出的MC51F003A4是一款高速低功耗1T周期8051内核8位增强型FLASH微控制器芯片,较传统8051相比,运行效率高。MC51F003A4的最高运行频率为16MHz,片上集成了16K字节FLASH ROM、1024字节EEPROM和512字节SRAM(256字节内部RAM加256字节外部RAM),内置1个高频RC振荡器和1个低频RC振荡器以及预留了1个外部32768Hz晶体...
High-performance 0.25-um CMOS technology for fast SRAMs A high performance 0.25 micrometers CMOS process has been developed for fast static RAMs. This technology features retrograde wells, shallow trench isolati... JD Hayden,TF Mcnelly,AH Perera,... - Microelectronic Device & Multilevel Interconne...
摘要: A nonvolatile 32 Mb ferroelectric random-access memory with 0.25 /spl mu/m design rules uses ATD control for SRAM applications and a common-plate folded bit-line cell scheme with current forcing latched sense amplifier for low noise level without cell area penalty....