library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity p_encoder is port(st,in0,in1,in2,in3,in4,in5,in6,in7:IN bit;yex,ys,y0,y1,y2:out bit);end p_encoder;architecture rtl of p_encoder is signal tmp_in:bit_vector(7 downto 0);signal tm...