board/xilinx/zynqmp/zynqmp-zcu102 psu_init_gpl.c psu_init_gpl.h 23,566 changes: 23,566 additions & 0 deletions 23,566 board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.c Load diff Large diffs are not rendered by default. 30,391 changes: 30,391 additions & 0 deletions 30,391 ...
dpll_prog is available in some psu_init files that's why this function should stay there. Signed-off-by: Michal Simek <michal.simek@xilinx.com>master v2021.07-rc2 … v2020.01-rc1 Michal Simek committed Oct 24, 2019 1 parent c126ba4 commit d8a6d1b Showing...
FSBL的作用主要是初始化PLL,DDR,MIO管脚分配,烧写FPGA,运行uboot等。核心代码代码位于psu_init.c中。 c)生成uboot d)使用bootgen工具生成BOOT.BIN文件,bootgen需要使用.bif文件做输入。bif指导那个文件用作输入,targets等 //arch = zynqmp; split = false; format = BIN the_ROM_image: { [fsbl_config]a53...
1) Create an FSBL Application in SDK. 2) Implement the patch from(Xilinx Answer 72113)if using Vivado 2018.3. 3) Run the FSBL, making sure to deselect "Run psu_init" in the Run/Debug Configurations: 4) Next, run your own Application, for example, Hello World, and be sure to again ...
(Answer 66218) Zynq UltraScale+ MPSoC — 由于 psu_int.c 和 psu_init.tcl 之间的差异, psu_init 流不起作用 2015.4 2016.1 (Answer 66219) Zynq UltraScale+ MPSoC — 通过在 JTAG 模式下配置处理器模块级软件控制的复位寄存器,使处理器脱离复位状态 2015.4 2016.1 (Answer 66295) Zynq UltraScale+ MPSoC...
2) 修改调试宏定义FSBL_DEBUG_INFO_VAL,可以在启动输出FSBL的一些状态信息,有利于调试,但是会导致启动时间变长。保存文件。可以看一下fsbl里包含了很多外设的文件,包括psu_init.c,qspi,sd等,大家可以再仔细读读代码。当然这个fsbl模板也是可以修改的,至于怎么修改根据自己的需求来做。
(Answer Record 66436) XSDB is not able to connect to PSU after successfully booting in SD mode on a ZCU102 board (Answer Record 66437) psu_post_config (from psu_init.tcl) sometimes hangs on a ZCU102 board (Answer Record 000036133) UltraScale/UltraScale+ Memory IP - Triaging PL MIG Cal...
#elif XPAR_PSU_DDR_0_S_AXI_BASEADDR #define DDR_BASE_ADDR XPAR_PSU_DDR_0_S_AXI_BASEADDR #endif #ifndef DDR_BASE_ADDR #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, / DEFAULT SET TO 0x01000000 #define MEM_BASE_ADDR 0x01000000 ...
在platform_zynqmp.c文件的platform_setup_timer函数中,首先采用XTtcPs_CfgInitialize函数对TimerInstance全局变量进行初始化,让TimerInstance和硬件的定时器0(ID为XPAR_PSU_TTC_0_DEVICE_ID)绑定,并让TimerInstance的寄存器地址和定时器0的地址绑定,同时初始化定时器0的寄存器(大都赋值为0),禁止定时器中断: ...
从Vivado 2019.1 起,IP integrator 中的 Zynq MPSoC PS 块包含 Tcl 参数 CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN,用于启用动态 FSBL SPD prom 读取和配置。 在全新和升级后的 ZCU102/106 板上将设置此参数。在psu_init.c和 FSBL 中禁用此参数将导致返回静态 DDR 配置操作。