We can only use the generate statement in concurrent verilog code blocks. This means we can’t include it within always blocks or initial blocks. In addition to this, we have to use either an if statement, case statement or a for loop in conjunction with the generate keyword. We use the...
Is your case statement supposed to be checking an_temp instead of sseg? That would make more sense. If so sseg is not even needed. Or are you saying that HEX0-HEX3 are supposed to be 4 bit inputs each, like HEX0[3:0] for the...
If your case statement was sized to the lower 2 bits it would cycle between all 4 values or you could put a "default:" case to use for all other addresses. You could prove this by reading a valid address(ie 9404) once then continuously reading invalid addresses and ge...
You're now assigning single bit values (HEX0-HEX3) to a 7-bit signal (sseg), so again, your final case statement is only going to work for sseg equal to 0 or 1. Is your case statement supposed to be checking an_temp instead of sseg? That ...
if (reset) count <= 0; else count <= count + 1; end reg [6:0]sseg_temp; //the 7 bit register to hold the data to output === Changed from 'reg' === reg [3:0]an_temp; //register for the 4 bit enable always @ (*) ...
If you do not mind, I request you to post here HW_TCL file for that component as well. Both Verilog file and HW_TCL file together would make it much easier for somebody else to take reference from that. Cheers, Bhaumik Translate 0 Kudos Copy link Reply Altera_For...
If you do not mind, I request you to post here HW_TCL file for that component as well. Both Verilog file and HW_TCL file together would make it much easier for somebody else to take reference from that. Cheers, Bhaumik Translate 0 Kudos Copy link Reply Altera_For...
If you do not mind, I request you to post here HW_TCL file for that component as well. Both Verilog file and HW_TCL file together would make it much easier for somebody else to take reference from that. Cheers, Bhaumik Translate 0 Kudos Copy link Reply Altera_For...
if (reset) count <= 0; else count <= count + 1; end reg [6:0]sseg_temp; //the 7 bit register to hold the data to output === Changed from 'reg' === reg [3:0]an_temp; //register for the 4 bit enable always @ (*)...
Is your case statement supposed to be checking an_temp instead of sseg? That would make more sense. If so sseg is not even needed. Or are you saying that HEX0-HEX3 are supposed to be 4 bit inputs each, like HEX0[3:0] for ...