Memory cell having a NBTI resistance is composed of NAND gates multiple ring. Plurality of NAND gates is one of the NAND gates in them is that the output has a 0 , the output consists of those remaining NAND gates to have a 1 . PMOS transistor of the memory cell suffer less ...
The NAND gate entry section which outputsPROBLEM TO BE SOLVED: To provide a switch circuit for a semiconductor circuit device, in which high voltage can be effectively transmitted, even under a low power supply voltage.金 度局
PROBLEM TO BE SOLVED: To provide a signal processing apparatus and method in which a picture quality is improved by displaying an input video signal quantized equally with or more than 8 bits on a screen with bits reduced as little as possible while minimizing its loss in a digital video ...
The present invention discloses a driving circuit in which capture by the NAND gate is achieved, and a shift register in which capture by the NAND gate is achieved. The drive circuit, which achieves capture by the NAND gate, comprises a plurality of cascaded shift register circuits, each ...
The delay circuit has a voltage source which supplies voltage to a delay chain comprising a pair of inverters (401,404), transistors (406,407), resistor (402), NAND gate (405) and capacitors (403,408), in response to the input signal (IN). Independent claims are also included for the...
PROBLEM TO BE SOLVED: To provide a voltage-controlled oscillator and a voltage controlled oscillating method capable of allowing a control voltage to be inversely proportional or directly proportional to an oscillation frequency, without complicating the configuration of a circuit.佐々木 博文...