The genvar keyword is a new data type, which stores positive integer values. It differs from other Verilog variables in that it can be assigned values and changed during compile or elaboration time. The index variable used in a generate loop must be declared as a genvar. A localparam is a...
I didn't know this kind of construction in Verilog, and I wonder if it wouldn't add confusion to a code if you start mixing it with the traditionnal vector representation... --- Quote End --- The main reason for use it is genvar j; generate for(j=$bits(regs.io.rw);j!=0...