This page contains tidbits on writing FSM in verilog, difference between blocking and non blocking assignments in verilog, difference between wire and reg, metastability, cross frequency domain interfacing, all about resets, FIFO depth calculation,Typica
The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. This approach allows for an entire clock period (except for the setup time of the second flip-flop) for metastable events in the first synchronizing flip-flop to resolve ...
multi-channel ADC. This is primarily used for the self monitoring of system voltages. In the final production revision, at least one channel of the ADC will also be available as a configuration option on the GPIO internal header so that users have an easier path to integrating analog sensors ...