电压电流（DCTEST）测试是指在设计和装配过程中筛选不良产品的过程，而老化测试（Burn-inTEST）是指在施加极端条件后进行测试，以提前检查可能存在不良产品的过程。只有通过这一过程，半导体芯片所在的电子设备才能获得无错误运行的可靠性。2) Main Test 通过DC &Test Burn in测试的产品将在室温和低温空间中进行电气特...
Semiconductor devices and wafer level burn-in test techniques include having such as an ASIC or the like attached to the interconnect substrate on which the test substrate mounting active electronic components, a plurality of the ASIC and the test wafer (WUT) is on implement the interconnection ...
Proven applications include: Full wafer functional, stress, and burn-in test of automotive ICs; low cost full wafer test of discrete or embedded memories; Learn more about Single Wafer Test and Burn-in Solutions. Multi Wafer Test and Burn-in Solutions The FOX-XP is a Multi-Wafer System burn...
in test mode entry signal according to the wafer burn-in address signal and a command signal from the command decoder, a shift registers configured to shift the wafer burn-in address signal according to the wafer burn-in test mode entry signal and a wafer burn-in clock signal, a wafer ...
A wafer burn-in test and a wafer test circuit for a semiconductor memory device which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state. HM Sung 被引量: 9发表: 2004年 Wafer burn-in...
operation of the sub word line driver, wherein a ground power source is applied to the first and second power lines during a normal operation, and the ground power source and a step-up power source are alternately applied to the first and second power lines during a wafer burn-in test ...
operation of the sub word line driver, wherein a ground power source is applied to the first and second power lines during a normal operation, and the ground power source and a step-up power source are alternately applied to the first and second power lines during a wafer burn-in test ...
WAFER BURN-IN TEST METHOD, WAFER BURN-IN TEST APPARATUS, AND SEMICONDUCTOR STORAGE DEVICE 来自 百度文库 喜欢 0 阅读量: 33 申请(专利)号: JP20050353523 申请日期: 2005-12-07 公开/公告号: JP2007157282A 公开/公告日期: 2007-06-21 申请(专利权)人: ELPIDA MEMORY INC 发明人:...
A burn-in test circuit of a semiconductor memory device with a first test circuit having output terminals connected to input terminals of a first half of plurality of word line drivers. A second test circuit has output terminals connecte... Jae-gu Roh,Soo-in Cho - US 被引量: 22发表: 19...
PURPOSE: A semiconductor memory device having built-in parallel test circuit is provided to reduce test time in a wafer level. CONSTITUTION: A memory cell array(100) has a plurality of memory cells, and a plurality of input/output line p... NJ Kim 被引量: 0发表: 2001年 Burn-in test ...