INFO: [VRFC 10-2263] Analyzing Verilog file "path_to_project/axi_master_example_v1_0/34c559c4/VHDL_sources/testbench_sources/axi_bfm_defines.v" into library xil_defaultlib ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [path_to_project/axi_master_exa...
问错误：[VRFC 10-2951]“WIDTH_DIFF”不是常量。ENGo语言的常量有个不同寻常之处。虽然一个常量可以...