voltage loop 美 英 un.电压波腹 网络电压回路;电压补偿功能分析 英汉 网络释义 un. 1. 电压波腹 例句 释义: 全部,电压波腹,电压回路,电压补偿功能分析 更多例句筛选
Close the channel and measure thevoltagewith a sensitive voltmeter. 闭合通道,利用一个灵敏的伏特计测量电压. 期刊摘选 There exist a relation of triangular wave curve betweenvoltageof tuned loop and external flux. 回路输出电压与外磁通为三角波曲线关系,再受静磁场作用时曲线移动,据此可测磁通量子. ...
我将在那里在6月20日希望附近所有是好能我转交资金您,并且您可能支付promat,在您不可能做它情况下? [translate] aloop in the complex vector and outer square of the voltage loop, is 圈在电压圈的复杂传染媒介和外面正方形,是 [translate] 英语翻译 日语翻译 韩语翻译 德语翻译 法语翻译 俄语翻译 阿拉伯语...
Problems arising due to interconnection are instability in voltage and inner circulation of current within micro grid. Such problems have been addressed by the use of inner loop controllers that is simple to implement and provides better performance as compared to other controllers such as conventional...
aholy evening 圣洁晚上[translate] aIn general, inner control loop 306 maintains the power delivered to the load as a function of the received power voltage, e.g., in an aircraft, the voltage range is from about 18 to 32 volts. Outer control loop 304 monitors a characteristic variable, e...
A pulse frequency modulation unit controls upper limit level and lower limit level for an output voltage of a DC-DC converter. A voltage mode control loop uses the upper and lower limit levels in a feedback loop to generate a control signal to enable and disable the converter circuit.收藏...
美 英 un.电压反馈 网络电压回授 英汉 网络释义 un. 1. 电压反馈 释义: 全部,,电压回授
4.Analysis of misoperation Caused by No-voltage in PT Secondary Loop of Microcomputer Protection一起微机保护装置压变二次三相交流电压失压误动的原因分析 5.Experimental Study of Compressive Buckling for an Axial Compressible Rod轴向可压缩压杆的压缩失稳实验研究 6.It can not require a pressure loss.它...
S Tertinek,A Teplinsky,O Feely - International Workshop on Nonlinear Maps & Their Applications 被引量: 2发表: 2007年 Phase-locked loops and synthesizers The phase detector, amplifier, and voltage-controlled oscillator (VCO) form a phase-locked loop (PLL) that is capable of locking on to ...
A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. The DLL incorporates ...