sanchuanhehe/MIPSproject_nexysPublic NotificationsYou must be signed in to change notification settings Fork0 Star4 Code Issues Files main MIPSproject.cache MIPSproject.gen MIPSproject.hw MIPSproject.ip_user_files MIPSproject.runs MIPSproject.sim ...
ERROR: [VRFC 10-3180] cannot find port 'rst' on this module [D:/CLAW/risc-v-flow-cpu-to-trace/claw_cpu.srcs/sim_1/new/top_sim.v:34] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step...