NA Fixed corner case bug in 2.5G transmit logic - MAC might not corrupt the TX frame if the user error indication is received at very early or very late stages of frame transmission v9.0 (Rev.2) v9.0 (Rev.4) (Answer Record 65947) LogiCORE Tri Mode Ethernet MAC v9.0 (Rev 3) - Ult...
1. Git clone Vitis AI 2.0 , from there you will need “DPU IP” and “ZCU102-DPU-TRD2.0.BSP”. 2. Create the VIVADO Block design with DPU IP. You can download the Tcl file of the VIVADO project, Block Design PDF, XSA and generate the project on your PC. 3. Here is the Block...