在编译xilinx工程时报错:[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_RO…
[Place 30-575]VIVADO 布局布线bug 开始怀疑是约束文件有问题,把输入引脚的位置错误约束了,但是并没有,DDR的输入时钟也是用的bank33,电平、引脚约束也没错(Alinx AX7325B开发板) 尝试按照建议添加 set_property CLOCK_DEDICATED_ROUTE BACKBONE,但是imple仍然报该错误,并且综合提示set property为空? 原代码中ddr参考...
配置好之后,编译代码,在Implementation阶段,提示: [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING...
[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highl...
During implementation, the Vivado tools place design elements onto device resources, route the design network, and optimize to reduce power and close timing. For more information, see the Vivado Design Suite User Guide: Synthesis (UG901) and Vivado Design Suite User Guide: Implementation (UG904)...