(Answer Record 63165) MIG 7 Series DDR2/DDR3 v2.2/2.3- Additional BUFG being added in "opt_design" on the "freq_refclk" can lead to minimum pulse width timing violations 2.3 2.3 Rev1 (Answer Record 60527) MIG 7 Series - Virtex-7 HT - Error is generated when trying to open MIG 7...
I've then installed WSL version 2: And if i then created a new MIG Block design, and try to open it, to customize this IP, it is stuck Hence, i can indeed reproduce the Vivado hang behaviour ONLY once i have WSL installed. Without WSL, all works fi...
For the same block design but without the input for den just using eoc as output. Kindly help me. Its been a while but I am still stuck at this spot. Thanks in advance. jpeyron Members 5.8k 171 LocationPullman Posted October 8, 2018 Hi @Newbiee, I do not have a lot of...