一、报错信息如下: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 9 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal in...
AI检测代码解析 [DRC UCIO-1] Unconstrained Logical Port: 10 out of 28 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause dama...
SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: clk, din, dout. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 翻译: 错误:[Drc 23-20]违反规则(UCIO-1)不受限制的逻辑端口-3个逻辑端口中的3个没有用户分配的特定位置约束(LOC)。这可能会导致I / O争用或与电路板电源或连接...
siteLOCconstraint defined.To allow bitstream creationwithunspecified pinlocations(not recommended),use set_propertySEVERITY{Warning}[get_drc_checksUCIO-1].Problem ports:clk,din,dout. 翻译: 错误:[Drc 23-20]违反规则(UCIO-1)不受限制的逻辑端口-3个逻辑端口中的3个没有用户分配的特定位置约束(LOC)。这...
方法1：set_property SEVERITY {Warning} [get_drc_checks NSTD-1]set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]set_property SEVERITY {Warning} [get_drc_checks UCIO-1]方法2：set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup ...
1. ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 3 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting ...
1、新建一个记事本,写下如下内容: set_property SEVERITY {Warning} [get_drc_checks NSTD-1] set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1] set_property SEVERITY {Warning} [get_drc_checks UCIO-1] 2、保存,且文件名为name.tcl,见图: ...
usb接口我没有使用,drc时检测没有约束,导致报错。根据上述提示将以下保存成tcl文件。 set_property SEVERITY {Warning} [get_drc_checks NSTD-1] set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1] set_property SEVERITY {Warning} [get_drc_checks UCIO-1]...
如果错误消息指出是[DRC NSTD-1]或[DRC UCIO-1]类型的错误,这通常意味着你的设计中存在未指定的I/O标准或未约束的逻辑端口。 解决方法是为这些端口添加I/O标准和引脚位置约束。例如,你可以在约束文件(XDC)中添加如下约束: xdc set_property IOSTANDARD LVCMOS33 [get_ports {clk}] set_property PACKAGE_PIN...
set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1] set_property SEVERITY {Warning} [get_drc_checks UCIO-1] 再重新生成即可。 8.Program and Debug:生成了下载文件后就可以去查看链接的电路板了,这里因为暂时还没有硬件,后续步骤以后再加上。