[DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal clk_50m_gen/inst/clk_in on the clk_50m_gen/inst/plle2_adv_inst/CLKIN1 pin of clk_50m_gen/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO. 二、报错原因 IBUFGDSc...
一、报错内容 [DRCREQP-1712]Inputclockdriver:UnsupportedPLLE2_ADVconnectivity.Thesignalclk_50m_gen/inst/clk_inontheclk_50m_gen/inst/plle2_adv_inst/CLKIN1pinofclk_50m_gen/inst/plle2_adv_instwithCOMPENSATIONmodeZHOLDmustbedrivenbyaclockcapableIO. 二、报错原因 IBUFGDSclk_inst(.O(clk),.I(clk_p...
63770 - Vivado - REQP-1817 DRC error with SGMII example design Description When Generating a bitfile from a 2014.4 Ethernet 1000BASE-X PCS/PMA or SGMII example design, the following DRC error is received: ERROR: [Drc 23-20] Rule violation (REQP-1817) IDELAYCTRL_RST_connects_to_CMT_LOCKED_...
63770 - Vivado - REQP-1817 DRC error with SGMII example design Description When Generating a bitfile from a 2014.4 Ethernet 1000BASE-X PCS/PMA or SGMII example design, the following DRC error is received: ERROR: [Drc 23-20] Rule violation (REQP-1817) IDELAYCTRL_RST_connects_to_CMT_LOCKED_...