[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 1400.000 MHz (CLKIN1_PERIOD, net 综合过了,implement时报这个错,找了半天原因,最后理解了下,大概意思是我给的时钟太快了,超过了最大值,将100M的时钟改成了50M,错误就消失了。但有一个疑问就是cameralink发送图像的输入时钟连100M都...
(Answer Record 60846) MIG 7 Series DDR3 - Kintex-7 -2L/-3L - Incorrect refclk frequency of 400MHz generated for designs operating above 1333 Mbps (667MHz) causes DRC error during implementation 2.1 v2.3 (Answer Record 61744) MIG 7 Series DDR3 - ECC Multiple errors are seen in hardware ...