wire [15 : 0] m_axis_data_tdata;//输出为16位,高8位是sin波形,低8位是cos波 wire m_axis_phase_tvalid; wire [31 : 0] m_axis_phase_tdata; assign valid = m_axis_data_tvalid; assign sin =m_axis_data_tdata[15:8]; assign cos =m_axis_data_tdata[7:0]; dds_ctl Udds_ctl( ...
.config_tdata(s_axis_config_tdata) ); dds_compiler_0 UDDS ( .aclk(aclk), // input wire aclk .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid .s_axis_phase_tdata(s_axis_phase_tdata), // input wire [31 : 0] s_axis_phase_tdata .s_axis_con...
wire[15:0]m_axis_data_tdata;//输出为16位,高8位是sin波形,低8位是cos波 wire m_axis_phase_tvalid; wire[31:0]m_axis_phase_tdata; assign valid=m_axis_data_tvalid; assign sin=m_axis_data_tdata[15:8]; assign cos=m_axis_data_tdata[7:0]; dds_ctl Udds_ctl( .aclk(aclk),//1...
assign m_data_cos = {~m_data_tdata[7],m_data_tdata[6:0]} ;//将输出转为有符号数据输出 cos //模块例化 //DDS_IP模块 dds_compiler_0 u_dds_0 ( .aclk (sys_clk ),// input wire aclk .s_axis_phase_tvalid (s_phase_tvalid ),// input wire s_axis_phase_tvalid .s_axis_phase...
.phase_tvalid(s_axis_phase_tvalid), .phase_tdata(s_axis_phase_tdata), .config_tvalid(s_axis_config_tvalid), .config_tdata(s_axis_config_tdata) ); dds_compiler_0 UDDS ( .aclk(aclk), // input wire aclk .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_pha...
phase_tdata <= phase_tdata + 10'd655; // (1k / 100k) * 2^16 =655 end else begin phase_tdata<=16'd0; end end dds_compiler_0 dds_inst( .aclk(clk_100K), .s_axis_phase_tvalid(1'b1), .s_axis_phase_tdata(phase_tdata), ...
开始查找原因,抓取DDS核的输入是否正确即s_axis_phase_tvalid和s_axis_phase_tdata是否正确,抓取的结果如下: 上图的中DDS核的输入不是绿色,而是橙色(目前还不知道橙色是什么,需要查资料)说明有问题,DDS核的输入没有拿到数据。 刚开始认为是IP库哪里没有配置对,于是决定下载到项目组正在调试的板子上进行验证程序...
phase_tdata(s_axis_phase_tdata), .config_tvalid(s_axis_config_tvalid), .config_tdata(s_axis_config_tdata) ); dds_compiler_0 UDDS ( .aclk(aclk), // input wire aclk .s_axis_phase_tvalid(s_axis_phase_tvalid), // input wire s_axis_phase_tvalid .s_axis_phase_tdata(s_axis...
dds_mix_wrapper inst_dds_mix_wrapper ( //.M_AXIS_DATA_0_tdata (M_AXIS_DATA_0_tdata), //.M_AXIS_DATA_0_tvalid (M_AXIS_DATA_0_tvalid), .P_0(P_0), .aclk_0 (aclk_0) ); endmodule 仿真环节 点击仿真simulation,并将两个DDS产生的波形信号添加到窗口中,找到相应的信号,右键添加到窗...
vivado提供了DDS IP核可以输出正余弦波形,配置方法如下 打开VIVADO,选择IP Catalog 输入DDS,找到DDS IP核,双击打开 打开IP核配置,parameter Selection选择System Parameters 设置System Parameters参数: Spurious Free Dynamic Range的设置,这个参数与输出数据的宽度相关。