I generate the output products for my design by selecting the Block Design in the hierarchy view and choosing "Generate Output Products" and then "OOC Per IP"At this point I get the following: export_simulation -of_objects [get_files C:/test/test.srcs/sources_1/bd/design_1/design_1.bd...
There is an error when synthesizing the IP core when using either OOC generation mode or as part of the complete design. For example: When synthesizing a design with an Ethernet Subsystem IP core, an error occurs related to a missing board.xdc file. ...
67850 - 2018.2 Vivado IP Flows - Validating an IP Integrator block design gives ERROR: [Designutils 20-414] HRTInvokeSpec … Number of Views2.13K 66984 - Vivado IP Flows - BRAM memory initialization in a user IP gives the following: "Critical Warning: [Synth 8-4445] c… Number of Views...