PORT (a_in : IN STD_LOGIC;a_out : OUT STD_LOGIC);END COMPONENT;
ENTITY实体名IS[GENERIC(参数表);][PORT(端口表);][BEGIN实体语句部分;]END[ENTITY][实体名]; 其中,GENERIC 是用于说明设计实体和其外部环境通信的对象,规定端口的大小、实体中子元件的数目、实体的延时特性等。只能用整数类型表示,如整型、时间型等,其他类型的数据不能逻辑综合。格式如下: 代码语言:javascript 代...
The following VHDL component declaration is located in theVHDL Design File (.vhd) DefinitionALTERA_PRIMITIVES_COMPONENTS.VHDlocated in the<Quartus®Primeinstallation directory>\libraries\vhdl\alteradirectory. component alt_outbuf_tri_diff generic ( io_standard : string := "NONE"; current_strength :...
rchitecture BehavioralofTempSensorCtlis-- TWI ControllercomponentdeclarationcomponentTWICtlgeneric//中间省略endBehavioral; 元件就是其他文件定义好的模块,比如元件component TWICtl,就是其他文件的模块,这里只是调用 componentTWICtlgeneric( CLOCKFREQ : natural :=50; --inputCLK frequencyinMHz ATTEMPT_SLAVE_UNBLOCK...
-- TWI Controller component declaration component TWICtl generic //中间省略 end Behavioral; 1. 2. 3. 4. 5. 6. 7. 元件就是其他文件定义好的模块,比如元件component TWICtl,就是其他文件的模块,这里只是调用 component TWICtl generic ( CLOCKFREQ : natural := 50; -- input CLK frequency in MHz ...
-- BUF_COMP component declaration: component BUF_COMP is generic (TIME_DELAY : TIME); port ( IN1 : in BIT; OUT1 : out BIT ); end component; begin -- instantiation of BUF_COMP component: DUT:BUF_COMP generic map (10 ns) port map (TEST1,TEST2); end STRUCT_BUF_TEST; -- Configura...
其中,GENERIC 是用于说明设计实体和其外部环境通信的对象,规定端口的大小、实体中子元件的数目、实体的延时特性等。只能用整数类型表示,如整型、时间型等,其他类型的数据不能逻辑综合。格式如下: GENERIC ([CONSTANT]属性名称:[IN]子类型标识[:=静态表达式],……); ...
-- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY ROMtb IS -- Component Declaration for the Unit Under Test (UUT) --GENERIC ( INIT_0 : bit_vector(15 downto 0) := X"0000" ); PORT (
GENERIC([CONSTANT]属性名称:[IN]子类型标识[:=静态表达式],……); PORT 关键字用于定义模块的端口,它的格式如下: PORT([SIGNAL]端口名称:[方向]类型标识[BUS][:=静态表达式],[SIGNAL]端口名称:[方向]类型标识[BUS][:=静态表达式],…[SIGNAL]端口名称:[方向]类型标识[BUS][:=静态表达式]); ...
-- BUF_COMP component declaration: component BUF_COMP is generic (TIME_DELAY : TIME); port ( IN1 : in BIT; OUT1 : out BIT ); end component; begin -- instantiation of BUF_COMP component: DUT:BUF_COMP generic map (10 ns) port map (TEST1,TEST2); end STRUCT_BUF_TEST; -- Configura...