For UDP, IP, and ARP support, useudp_complete(1G) orudp_complete_64(10G/25G). Top level gigabit and 10G/25G MAC modules areeth_mac_*, with various interfaces and with/without FIFOs. Top level 10G/25G PCS/PMA PHY module iseth_phy_10g. Top level 10G/25G MAC/PCS/PMA combination ...
This repository is for storing open-source Verilog modules that use the AXI4, AXI4-Lite, and AXI4-Stream interfaces. When a core is optimized around a specific architecture, there shall be an additional parameter, ARCH, which will contain the name of the architecture used. A list of archite...