Setting the property 'Library' on a Verilog or System Verilog file is ignored by Synthesis tool. Synthesis places all Verilog and System Verilog files in a default library. You may use set_msg_config tcl command to suppress the above warning message/limit them to a ...
Dear Sir, I'm working on a simulation for DDR3 on ncverilog. I got an error as below that some encryption files seem missed in library. How