The name of the parser: verilog.c The command line you used to run ctags: $ ctags --options=NONE foo.sv The content of input file: foo.sv typedef bit[31:0] int32_t; module mod( input bit clk, input int32_t a ); endmodule The tags output ...
verilog-mode
And for specify the cell bindings, I use the Table View in Hierarchy editor and force the view referenced by the generate loop to use the schematic view. I make sure the REF_CELL only includes two views: schematic and symbol. So, I hope the AMS can auto-detect that there is only one...