Wenjiew/verilog-ethernet 代码 Issues 0 Pull Requests 0 Wiki 统计 流水线 服务 Gitee Pages JavaDoc PHPDoc 质量分析 Jenkins for Gitee 腾讯云托管 腾讯云 Serverless 悬镜安全 阿里云 SAE Codeblitz 我知道了,不再自动展开 标签 Tags Releases 功能基于仓库中的历史标记 建议使用类似 V1.0 的版本标记作为 ...
Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G...
GitHub - alexforencich/verilog-ethernet: Verilog Ethernet components for FPGA implementation 用于1G、...
HDL Bits Solution RISC-V处理器篇 香山开源高性能处理器 木心处理器 Hummingbirdv2 E203 Core and SoC...
ethernet controller (GbE) multi-processing (SMP) network on chip (NoC) rv64i support (not so easy as it appears...) dynamic bus sizing and big-endian support user/supervisor modes debug support misaligned memory access bridge for 8/16/32-bit buses ...
###[ Ethernet ]### dst = 33:32:33:44:55:66 src = 33:22:22:34:56:33 type = IPv4 ###[ IP ]### version = 4 ihl = 5 tos = 0x0 len = None id = 1 flags = frag = 0 ttl = 64 proto = udp chksum = None src = 127.0.0.1 ...
高达256 Kbit的用户闪存和240 Kbit sysMEMTM嵌入式块RAM 高达334个可热插拔的IO，可防止额外漏电 通过...
让我们直接打开github verilog主题榜单top 10：Build software better, together Paddle-Lite百度飞浆深度...
更新：v0.2 版本，支持 64 位总线，并在 FPGA 平台上进行了性能分析，最高吞吐接近 2Gbps。v0.3 ...
GitHub repository:https://github.com/alexforencich/verilog-ethernet Introduction Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for...