The attached Verilog file declares the signal "clk" twice, once as an input and once in the body, but no error message is displayed. A more complicated module with this bad design resulted in error messages that didn't make sense (modules not being recognized or required).Contributor...
Add --top option as alias of --top-module. Add LATCH and NOLATCH warnings (#1609) (#2740). [Julien Margetts] Remove Unix::Processors internal test dependency. Report UNUSED on parameters, localparam and genvars (#2627). [Charles Eric LaForest] Add error on real to non-real output pin...
*** The default l2 scope name is now the same as the top-level module. (#1050) Use "--l2-name v" for the historical behavior. *** Add --l2-name option for controlling "v" naming. *** Fix --output-split of constructors. (#1035) [Johan Bjork] *** Fix removal of empty pa...
Add --top option as alias of --top-module. Add LATCH and NOLATCH warnings (#1609) (#2740). [Julien Margetts] Remove Unix::Processors internal test dependency. Report UNUSED on parameters, localparam and genvars (#2627). [Charles Eric LaForest] Add error on real to non-real output pin...
Add --top option as alias of --top-module. Add LATCH and NOLATCH warnings (#1609) (#2740). [Julien Margetts] Remove Unix::Processors internal test dependency. Report UNUSED on parameters, localparam and genvars (#2627). [Charles Eric LaForest] Add error on real to non-real output pin...