Verilator is failing a simulation that Questa and VCS are passing. I eventually tracked the discrepancy down to a cache with four ways, each containing tag memories. The Verilog writes to the memory in way 0. In Questa, the way 0 memory changes. In Verilator, the way 2 memory changes....
use the version number instead of git describe ./configure --prefix /CAD_DISK/verilator/`git describe | sed "s/verilator_//"` After installing you'll want a module file like the following: set install_root /CAD_DISK/verilator/{version-number-used-above} unsetenv VERILATOR_ROOT prepend-...
复制 %Error:clock_pix.sv:29:5:Cannot find file containing module:'MMCME2_BASE'29|MMCME2_BASE#(|^~~~%Error:clock_pix.sv:29:5:This may be because there's no search path specifiedwith-I.29|MMCME2_BASE#(|^~~~...Lookedin:MMCME2_BASEMMCME2_BASE.vMMCME2_BASE.sv obj_dir/MMCME2_BA...