scenario generation, transaction-level channels, transactors and messaging services. They also made extensive use of SystemVerilog assertions (SVA), both custom-written and selected from the Synopsys SVA assertion-checker library. One of the most valuable features of the resulting...
#${VCS_HOME}/packages/aip/DDR2_AIP/src/Snps_DDR2_Checker.sv \ -assert enable_diag \ +incdir+.+${VCS_HOME}/packages/aip/DDR2_AIP/src/ \ ./source/svtb/platform_tb/env/Snps_DDR2_Bind.sv \ +incdir+../BP062-BU-01000-r0p0-00rel0/sva \ +incdir+../BP062-BU-01000-r0p0-00rel...
. Using VCS Checker Library . . . . . . . . . . . . . . . . . . . . . . . . . . Instantiating SVA Checkers in Verilog . . . . . . . . . . . . . . . Binding SVA to a Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
noUI -error=PCWM-L -error=noZMMCM -timescale=1ns/10ps -quiet -q +rad +v2k +vcs+lic+wait +vc+list -f /home/chipyard/work/chipyard/chipyard/sims/vcs/generated-src/chipyard.TestHarness.RocketConfig/sim_files.common.f -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext ...
#${VCS_HOME}/packages/aip/DDR2_AIP/src/Snps_DDR2_Checker.sv \ -assert enable_diag \ +incdir+.+${VCS_HOME}/packages/aip/DDR2_AIP/src/ \ ./source/svtb/platform_tb/env/Snps_DDR2_Bind.sv \ +incdir+../BP062-BU-01000-r0p0-00rel0/sva \ ...
#${VCS_HOME}/packages/aip/DDR2_AIP/src/Snps_DDR2_Checker.sv \ -assert enable_diag \ +incdir+.+${VCS_HOME}/packages/aip/DDR2_AIP/src/ \ ./source/svtb/platform_tb/env/Snps_DDR2_Bind.sv \ +incdir+../BP062-BU-01000-r0p0-00rel0/sva \ ...
. Using Standard Checker Library . . . . . . . . . . . . . . . . . . . . . . Instantiating SVA Checkers in Verilog . . . . . . . . . . . . . . . Binding SVA to a Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . Inlining ...
#${VCS_HOME}/packages/aip/DDR2_AIP/src/Snps_DDR2_Checker.sv \ -assert enable_diag \ +incdir+.+${VCS_HOME}/packages/aip/DDR2_AIP/src/ \ ./source/svtb/platform_tb/env/Snps_DDR2_Bind.sv \ +incdir+../BP062-BU-01000-r0p0-00rel0/sva \ ...
#${VCS_HOME}/packages/aip/DDR2_AIP/src/Snps_DDR2_Checker.sv \-assert enable_diag \+incdir+.+${VCS_HOME}/packages/aip/DDR2_AIP/src/\ ./source/svtb/platform_tb/env/Snps_DDR2_Bind.sv \+incdir+../BP062-BU-01000-r0p0-00rel0/sva \+incdir+../BP062-BU-01000-r0p0-00rel0/verilo...
#${VCS_HOME}/packages/aip/DDR2_AIP/src/Snps_DDR2_Checker.sv \ -assert enable_diag \ +incdir+.+${VCS_HOME}/packages/aip/DDR2_AIP/src/ \ ./source/svtb/platform_tb/env/Snps_DDR2_Bind.sv \ +incdir+../BP062-BU-01000-r0p0-00rel0/sva \ ...