In VSIM : vcs: command not found make: *** [simv-rocketchip-DefaultConfig] Error 127 Hello, When I run make in the vsim directory, it yields the following: mkdir -p /home/alpha/rocket-chip/vsim/generated-src/ cd /home/alpha/rocket-chip && java -Xmx2G -Xss8M -XX:MaxPermSize=256...
Hello, I am trying to simulate the rocket chip Verilog using cadence simulator instead of vcs (cd vsim;make run) I would like to know what to modify to do so! … is there an example of the makefrag and other files to modify somewhere!! Thanks for your help Rgds...
@$(TEST)\(`grep -c 'UVM_ERROR : $(N_ERRS)' vcs_sim.log`-eq1\)-a \ \(`grep -c 'UVM_FATAL : $(N_FATALS)' vcs_sim.log`-eq1\)clean:rm-rf*~csrc core simv*vc_hdrs.h ucli.key urg**.log 5. 波形 编译log Verdi加载Fsdb文件 波形效果...
export_simulation -lib_map_path "." -force -directory "./scripts2" -simulator ies ERROR: [exportsim-Tcl-4] Export simulation is not supported for 'ies' on this platform. export_simulation -lib_map_path "." -force -directory "./scripts2" -simulator vcs ...
@$(TEST)\(`grep -c 'UVM_ERROR : $(N_ERRS)' vcs_sim.log`-eq1\)-a \ \(`grep -c 'UVM_FATAL : $(N_FATALS)' vcs_sim.log`-eq1\)clean:rm-rf*~csrc core simv*vc_hdrs.h ucli.key urg**.log 5. 波形 编译log Verdi加载Fsdb文件 ...
Impact:rtl Tell us about your environment: Chipyard Version: 1.3.0 OS: Linux 4.18.0-193.19.1.el8_2.x86_64 (Red Hat) Other: gcc version 8.3.1 20191121 (Red Hat 8.3.1-5) (GCC) VCS script version E-2011.03 What is the current behavior?