2.0时,约束为HIGH,1.8V 约束为normal。 (2)、根据实际硬件...} [get_iobanks 33]。 (2)、匹配电阻,选择40。7、 说明:如果是自己画的电路图,自定义的引脚,选择固定引脚选项,根据PCB将引脚映射完成。 8、 说明:约束文件中,当实际的VCCAUX_IO为
7 series FPGAs include an improved I/O driver structure allowing a higher pre-driver voltage (Vccaux_io) to achieve higher data rates. Vccaux_io is a separate rail providing power to the I/O circuitry in the High Performance banks. Vccaux_io must be set to 2.0V to achieve higher data ...