328907-002 Introduction—Processor Term MLC MSI MSL MSR NCTF ODT OLTM PCG PCH PECI Ψ ca PEG PL1, PL2 PPD Processor Processor Core Processor Graphics Rank SCI SF SMM SMX Storage Conditions SVID TAC TAP Description Mid-Level Cache Message Signaled Interrupt Moisture Sensitive Labeling Model Specifi...
Terminology (Sheet 3 of 3) Term Rank RDIMM RTID SCI SKU SMBus SSE STD Storage Conditions STR SVID TAC TCC TDP TLP TSOD UDIMM Uncore Unit Interval VCCD VCCIN VCCIO_IN VSS x1 x16 x4 x8 Description A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. Th...
EECTACHP CTAAHP FFYYWWLL YYWWLL GG HH JJ Figure4BallassignmentCEAA,CFAC,CTAA,andCTACpacket(topsideview) Note:HP=Buildcode,YYWWLL=Trackingcode Solderballsnotvisibleonthetopside.DotdenotesA1corner. Page17 nRF51822ProductSpecificationv3.3 BallfunctionsCEAA,CFAC,CTAA,andCTAC BallNameFunctionDescriptio...
Terminology (Sheet 3 of 3) Term Rank RDIMM RTID SCI SKU SMBus SSE STD Storage Conditions STR SVID TAC TCC TDP TLP TSOD UDIMM Uncore Unit Interval VCCD VCCIN VCCIO_IN VSS x1 x16 x4 x8 Description A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These ...