virtual function void build(); //与build phase不同,这仅仅是一个建立函数 reg_data = uvm_reg_field::type_id::creat("reg_data"); //new reg_field reg_data.configure(); //可以定义该field在这个reg中的具体位置,操作方式,是否有复位值 endfunction //是否可以随机化等。 function void sample_val...
size,has_coverage9super.new(name,16,UVM_NO_COVERAGE);10endfunction1112virtualfunctionvoid build();13reg_data=uvm_reg_field::type_id::create("reg_data");14//parameter:parent,size,lsb_pos,access,volatile,reset
rgm.chnl1_ctrl_reg.peek(status, data, .parent(this)); rgm.chnl1_ctrl_reg.poke(status, 'h22, .parent(this)); rgm.chnl1_ctrl_reg.peek(status, data, .parent(this)); //pre-defined methods read_reg()/write_reg() read_reg(rgm.chn12_ctrl_req, status, data, UVM_BACKDOOR); write...
uvm_reg_data_t expected[]; int max; fifo_reg FIFO; phase.raise_objection(this); `uvm_info("Test", "Resetting DUT and Register Model...", UVM_LOW) begin dut_reset_seq rst_seq; rst_seq = dut_reset_seq::type_id::create("rst_seq", this); rst_seq.start(null); end regmodel.re...
classmy_regextendsuvm_reg;randuvm_reg_fielddata;`uvm_object_utils(my_reg)virtualfunctionvoidbuild();data=uvm_reg_field::type_id::create("data");//parameter: parent, size, lsb_pos, access, volatile, reset value, has_reset, is_rand, individually accessibledata.configure(this,16,0,"RW",1...
virtual function bit predict (uvm_reg_data_tvalue, uvm_reg_byte_en_tbe=-1, uvm_predict_ekind=UVM_PREDICT_DIRECT, uvm_path_epath=UVM_FRONTDOOR, uvm_reg_mapmap=null, stringfname="", intlineno=0) Update the mirrored value for this register. ...
rand uvm_reg_data_t value Mirrored field value. This value can be sampled in a functional coverage model or constrained when randomized. Initialization new function new(stringname="uvm_reg_field") Create a new field instance This method should not be used directly. The uvm_reg_field::type_...
(3) uvm_config_db与uvm_resource_db共享同一套database; 因此可能会出现通过uvm_config_db::set()往database中存入信息,但用uvm_resource_db::read_by_name()从database中读取信息; uvm_resource_db#(type)::set("scope", "name", value, accessor); //path=scope+name, default value of accessor ...
typedef class uvm_reg_indirect_data; 除了声明了基本的寄存器模型外,还定义了一些全局变量和枚举的定义: //Type: uvm_hdl_path_slice///Slice of an HDL path///Struct that specifies the HDL variable that corresponds to all//or a portion of a register.///path - Path to the HDL variable.//of...
(stringname="R");super.new(name,8,UVM_NO_COVERAGE);endfunction:newvirtualfunctionvoidbuild();this._dummy=uvm_reg_field::type_id::create("value");this._dummy.configure(this,8,0,"RW",0,8'h0,1,1,1);endfunction:build`uvm_object_utils(reg_R)endclass:reg_Rclassblock_Bextendsuvm_reg...