reg_mem_addr.add_hdl_path_slice(“reg_mem_addr”, 0, 32); (2) The lock_model() is missing. This belongs to the register model. It si the last line of the build function of the register block; (3) This is optional you can set the uvm_hdl_path for RTL and for GATE like this...
Well dig a little inside uvm_reg and found the following 👍 {%- for field in node.fields() %} {%- if field.get_property('hdl_path_slice') is none -%} {%- elif field.get_property('hdl_path_slice')|length == 1 %}
Checks that the given HDL path exists. Returns 0 if NOT found, 1 otherwise. uvm_hdl_deposit(string path, uvm_hdl_data_t value) Sets the given HDL path to the specified value. Returns 1 if the call succeeded, 0 otherwise. uvm_hdl_data_t的定义在uvm源码中如下: dpi/uvm_hdl.svh文件中...