UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_resource_db.svh(121) @ 500000: reporter [CFGDB/GET] Configuration ‘uvm_test_top.env_h.e_apb_agent_h.sequencer.post_shutdown_phase.default_sequence’ (type class uvm_pkg::uvm_object_wrapper) read by uvm_test_top.env_h.e_apb_agent_h.sequ...
1.create_item 产生seq_item(factory) 2.wait_for_grant向sqr发出request,和等sqr的grant; sqr返回grant给seq 3.random seq_item ,然后send_request把seq_item 发给sqr.这个过程不消耗仿真时间,然后seq进入wait_for_item_done()的阻塞性等待状态,直到获取drv的response。 sqr的REQ FIFO会把seq_item转给drv。 dr...
class chnl_trans extends uvm_sequence_item; rand bit[31:0] data[]; rand int ch_id; rand int pkt_id; rand int data_nidles; rand int pkt_nidles; bit rsp; constraint cstr{ soft data.size inside {[4:32]}; foreach(data[i]) data[i] == 'hC000_0000 + (this.ch_id<<24) + (...