if(hier == UVM_NO_HIER || m_parent_map ==null) returnm_sequencer; returnm_parent_map.get_sequencer(hier); endfunction // get_adapter function uvm_reg_adapter uvm_reg_map::get_adapter(uvm_hier_e hier=UVM_HIER); if(hier == UVM_NO_HIER || m_parent_map ==null) returnm_adapter;...
functionvoiduvm_reg_block::get_registers(refuvm_reg regs[$], input uvm_hier_e hier=UVM_HIER);foreach(this.regs[rg]) regs.push_back(rg);if(hier ==UVM_HIER)foreach(blks[blk_]) begin uvm_reg_block blk=blk_; blk.get_registers(regs); end endfunction: get_registers functionvoiduvm_re...
uvm_hier_object可以继承于uvm_object,或者任何一个uvm_object的子类。uvm_hier_object新增的参数和方法: 新增参数:uvm_object类型的m_parent,m_children和m_children_by_handle。 新增传递parent方法:set_parent(uvm_object parent)。 新增children遍历方法:get_children,get_child,get_num_children等。 实现uvm_hie...
使验证环境更加稳定，提升tap out 成功率。所以，UVM也是基于SV的一种验证方法学，方便快捷的将功能模块...
} uvm_hier_e;//Enum: uvm_predict_e///How the mirror is to be updated///UVM_PREDICT_DIRECT - Predicted value is as-is//UVM_PREDICT_READ - Predict based on the specified value having been read//UVM_PREDICT_WRITE - Predict based on the specified value having been written//typedef enum...
// Enum: uvm_status_e // // Return status for register operations // // UVM_IS_OK - Operation completed successfully // UVM_NOT_OK - Operation completed with error // UVM_HAS_X - Operation completed successfully bit had unknown bits.// typedef enum { UVM_IS_OK,UVM_NOT_OK...
classhier_seqextendsuvm_sequence;`uvm_object_utils(hier_seq) function new(string name = "hier_seq"); super.new(name); endfunction task body(); bus_trans t1,t2; flat_seq s1,s2;`uvm_do_with(t1,{length==2;})fork`uvm_do_with(s1, {length == 5;})`uvm_do_with(s2,{length==8;...
`uvm_object_utils(hier_seq) function new(string name = "hier_seq"); super.new(name); endfunction task body(); bus_trans t1,t2; flat_seq s1,s2; `uvm_do_with(t1, {length == 2;}) fork `uvm_do_with(s1, {length == 5;}) ...
然后crc_error 是 UVM_ALL_ON|UVM_NOPACK,而 crc 是 UVM_ALL_ONUVM打印信息控制get_report_verbosity_level()set_report_verbosity_level(UVM_HIGH)只对当前调用的 component 起作用set_report_verbosity_level_hier(UVM_HIGH)对当前及下面所有的component 起作 30、用simv +UVM_VERBOSITY=UVM_HIGH命令行方式 ...
从hier_seq::body()来看,它包含有 bus_trans t1, t2 和 flat_seq s1, s2, 而它的层次关系就体现在了对于各个 sequence/item 的协调上面。例码中使用了'uvm_do_ with 宏,这个宏完成了三个步骤: • sequence 或 item 的创建; • sequence 或 item 的随机化; ...