Step1: 对每个寄存器进行定义 Step2: 将寄存器放入register block容器中,并加入到对应的Address Map Step3: 创建Register Adapter Step4: 顶层reg block对象的创建及使用 Step5: 将Address Map连接到Bus sequencer和Adapter Step6: 在sequence或其他component中使用寄存器模型 4 寄存器访问方法 前门访问和后面访问的区别 ...
// Address decode for the select lines: // Address decode for the select lines: int no_select_lines = 1; int apb_index = 0; // Which PSEL is the monitor connected to logic[31:0] start_address[15:0]; logic[31:0] range[15:0]; //--- // Methods //--- // Standard UVM Me...
txn=wb_txn::type_id::create("txn");// create a new wb_txntxn.adr=wb_bus_if.s_addr;// get addresstxn.count=1;// set count to one read or writeif(wb_bus_if.s_we)begin// is it a write?txn.data[0]=wb_bus_if.s_wdata;// get datatxn.txn_type=WRITE;// set op typewhi...
tasksfr_driver::run_phase(uvm_phasephase);sfr_seq_itemitem;foreverbeginseq_item_port.get_next_item(item);if(SFR.reset==1)beginSFR.re<=0;SFR.we<=0;SFR.address<=0;SFR.write_data<=0;wait(SFR.reset==0);endelsebegin@(posedgeSFR.clk);SFR.address=item.address;SFR.we<=item.we;SFR.wr...
(3) 如果寄存器map到多个uvm_address_map,在调用uvm_reg的write/read task进行前门访问时,需要指定uvm_reg_map参数; 回到顶部 2.2 write (frontdoor)的源码 (1) uvm_reg::write (1.1) FRONTDOOR write操作最终会转换为uvm_reg_map的do_write任务; ...
1functionvoid uvm_reg_map::set_base_addr(uvm_reg_addr_t offset);2if(m_parent_map !=null)begin3m_parent_map.set_submap_offset(this, offset);4end5elsebegin6m_base_addr =offset;7if(m_parent.is_locked())begin8uvm_reg_map top_map =get_root_map();9top_map.Xinit_address_mapX();10...
tasksfr_driver::run_phase(uvm_phasephase);sfr_seq_itemitem;foreverbeginseq_item_port.get_next_item(item);if(SFR.reset==1)beginSFR.re<=0;SFR.we<=0;SFR.address<=0;SFR.write_data<=0;wait(SFR.reset==0);endelsebegin@(posedgeSFR.clk);SFR.address=item.address;SFR.we<=item.we;SFR.wr...
irtual protected taskdrive_address_phase (apb_transfer trans); extern virtual protected task drive_data_phase(apb_transfer trans);endclass : apb_master_driverfunction void apb_master_driver:connect_phase(uvm_phasephase); super.connect_phase(phase); if (!uvm_config_db#(virtual apb_if):get(...
在例化uvm_reg_block的component中也例化uvm_reg_map，然后调用其configure函数，配置base address，大...
// Wishbone base address of MACbit[47:0]m_mac_eth_addr;// Ethernet address of MACbit[47:0]m_tb_eth_addr;// Ethernet address of testbench for sends/receivesint m mem slave size;// Size of slave memory in bytesint unsigned m_s_mem_wb_base_addr;// base address of wb memory for...