classwb_m_bus_driverextendsuvm_driver#(wb_txn,wb_txn);...localvirtualwb_m_bus_driver_bfmm_bfm;// Virtual Interfacewb_configm_cfg;functionvoidbuild_phase(uvm_phasephase);if(m_config==null)if(!uvm_config_db#(wb_config)::get(this,"","wb_config",m_cfg))begin`uvm_fatal(...)endm_...
class my_driver extends uvm_driver; //继承uvm库中的uvm_driver类 `uvm_component_utils(my_driver) //将my_driver类注册到factory virtual my_if vif; //声明driver的interface, interface my_if的定义这里不再介绍 extern virtual function void build_phase(uvm_phase phase); extern virtual task void mai...
classs base_test extends uvm_test; my_config cfg;functionvoid build_phase(uvm_phase phase); super.build_phase(phase); cfg= my_config::type_id::create("cfg"); uvm_config_db#(my_config)::set(this,"env.i_agt.drv","cfg", cfg); uvm_config_db#(my_config)::set(this,"env.i_agt....
在test.env中get:class my_env extends uvm_env;my_config cfg;...function void bulid_phase(uvm_phase phase);...if(!uvm_config_db#(my_config)::get(this,"","cfg",cfg))begin`uvm_fatal(" get config object failed")end...endfunctionendclass ...
uvm_config_db#(uvm object)::get(this,"", "cfg", tmp); void'($cast(cfg, tmp)); `uvm info ("SETVAL", $sformatf("cfg.vallis %d afterget",cfg.vall}, UVM_LOW) endfunction endclass class test1 extends uvm_test; `uvm_componen_utils(test1) ...
endclass initialbegin run_test("test1"); end endmodule 输出结果: UVM_INFO@0: reporter [RNTST]Runningtest test1... UVM_WARNING@0: uvm_test_top [UVM/CFG/SET/DPR]get/set_config_*APIhas been deprecated.Useuvm_config_db instead.
`uvm_warning("GETCFG","cannot get config object from config DB") cfg = apb_config::create("cfg"); end // get virtual interface if( !uvm_config_db#(virtual apb_if)::get(this,"","vif", vif)) begin `uvm_fatal("GETVIF","cannot get vif handle from config DB") ...
类: UVM中几乎所有的东西都是用类(class)来实现的,所以,搭建uvm平台第一条原则,所有的组件都用类来完成。 基于UVM类: 当要实现一个功能时,首先应该想到的是从UVM的某个类派生出一个新的类来实现期望功能,所以,搭建uvm平台第二条原则,所有的组件应该派生自uvm类。
uvm_config_db#(uvm_sequence_library_cfg)::set(this. "env.i_agt.sqr.main_phase", "default_sequence.config", cfg); or simple_seq_library seq_lib; super.build_phase(phase); seq_lib = new("seq_lib"); seq_lib.selection_mode = UVM_SEQ_LIB_RANDC; seq_lib.min_random_count = 10; ...
endclass ``` ### 步骤3:使用uvm_set_config_int函数设置配置参数 最后,我们使用uvm_set_config_int函数来设置配置参数。 ```verilog module testbench; my_config cfg; initial begin // 实例化配置对象 cfg = new(); // 设置整型参数 uvm_config_db#(int)::set(null, "*", "my_config.my_int_...