A microprocessor of the superscalar pipelined type, having speculative execution capability, is disclosed. Speculative execution is under the control of a fetch unit having a branch target buffer and a return address stack, each having multiple entries. Each entry includes an address value ...
Maxim's DS1232 MicroMonitor chip is a highly integrated solution to add power-on reset delay, a pushbutton reset controller, robust power failure monitoring, and watchdog timer functionality to your microprocessor system with the addition of a single chip. The ch...
() corresponds to the semantics of the inner parallel region. For the inner parallel region in the routine nestedpar, the variable id is a shared stack variable for the inner parallel region. Therefore, it is accessed and shared by all threads through the T-entry argument id_p. Note that...
A computer system includes a number of storage elements encoded with space selection instructions and at least one current-space storage element that together allow a computer to address a larger number of devices than allowed by a limited number of address terminals on the computer. Specifically, ...
Special purpose heaps are created to store different classes of data to which different rules apply. A library of functions is provided which is designed to respect the different classes of rules that
A microprocessor of the superscalar pipelined type, having speculative execution capability, is disclosed. Speculative execution is under the control of a fetch unit having a branch target buffer and a return address stack, each having multiple entries. Each entry includes an address value ...
3972024 Programmable microprocessor 1976-07-27 Schroeder et al. 364/200 3958221 Method and apparatus for locating effective operand of an instruction 1976-05-18 Serra et al. 364/200 3839705 DATA PROCESSOR INCLUDING MICROPROGRAM CONTROL MEANS 1974-10-01 Davis et al. 364/200 3689895 MICRO-PROGRAM ...
A fully programmable, graphics microprocessor is disclosed which is designed to be embodied in a removable external memory unit for connection with a host information processing sys
Use codes representative of uses of calls are defined as a part of a network numbering plan, and a route or a destination for a call is selected in full or in part on the basis of the use code dialed by a caller in conjunction with the called number via a call-processing arrangement ...
A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. The second