doi:EP0296247 A1IMOTO KATSUYUKISANO HIROHISATSUSHIMA H HITACHI-KOYASUDAI-AEPEP0296247A1 1988年7月5日 1988年12月28日 Hitachi, Ltd. Optical multiplexer/demultiplexer and use of the same in an optical moduleSee also references of EP0296247A1
Introduction: This experiment will demonstrate the properties and illustrate some of the applications of digital multiplexers and demultiplexers through th... 被引量: 0发表: 0年 MULTIPLEXER AND DEMULTIPLEXER FOR PULSE CODE CHANNELS Introduction: This experiment will demonstrate the properties and illustrat...
Compact multi-frequency lasers are realized by combining III-V based optical amplifiers with silicon waveguide optical demultiplexers using a heterogeneous... S Keyvaninia,S Verstuyft,S Pathak,... - 《Optics Express》 被引量: 30发表: 2013年 Mode Multiplexer/Demultiplexer Based on a Partially El...
HD74LV2G53AUSE L53 HITACHI 05+ SSOP8 1500 集成电路ICIntegrated Circuit(IC)-开关ICSwitch IC-多路复用器/多路分解器Multiplexer/Demultiplexer 查看 HD74LV2G66AUSE 1A1 HITACHI 05+ SSOP-8 400 集成电路ICIntegrated Circuit(IC)-开关ICSwitch IC-模拟开关Analog Switch 查看 HD74LV2G74AUSE L74 HITACHI 05...
HD74LV2G34AUSE RENESAS Triple Noninverters 获取价格 HD74LV2G53A RENESAS 2-channel Analog Multiplexer / Demultiplexer 获取价格 HD74LV2G53AUSE RENESAS 2-channel Analog Multiplexer / Demultiplexer 获取价格 HD74LV2G66A RENESAS 2-channel Analog Switch 获取价格 HD...
The select input of multiplexer 890 is the sector value θ modified by an LPF delay factor, compensates for phase delays introduced by LPF 860. This modification is schematically indicated by an adder 892, receiving both the θ and LPF delay signals, and providing a select input to ...
In one aspect, duplicated same-function circuit blocks are replaced with a switch controlled by an alignment control signal to operate as a multiplexer or demultiplexer. In another aspect, multiple different-function circuit blocks which generally have no temporal overlap of their active operation are...
Voltage in case of said light emission and non-light emission is A/D-converted 8 through a multiplexer 7, and is applied to a demultiplexer 9. To a block 14, a block 26 and a block 73, Tvc of said reset time, Tvs of an exposure time and a contrast data DELTA cs are provided, ...
At least one of the receiving systems serves a plurality of living units (75). The common equipment includes a digital receiver (103) processing each multiplexer channel to capture a digital transport stream therefrom and a demultiplexer (105) for separating out the digital signals. A switch (...
Figure 16 - Programmable digital delay block diagram The programmable digital delay block, shown in Figure 16, is a set of delay stages connected in series with each delay-stage output driving both the next delay-stage input and an input on a multiplexer. The delay stages could be simple ...