if (num_lanes == 1 || num_lanes == 2) { udphy->mode |= UDPHY_MODE_USB; udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false; } @@ -1115,18 +1104,17 @@ static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) ...
2 changes: 1 addition & 1 deletion 2 drivers/phy/rockchip/phy-rockchip-usbdp.c Original file line numberDiff line numberDiff line change @@ -1285,7 +1285,7 @@ static const struct phy_ops rk_udphy_dp_phy_ops = { static int rk_udphy_usb3_phy_init(struct phy *phy)...
USB 3.1 switches, bandwidths 11.5GHz, insertion loss -0.5dB, and return loss -27dB, ultra-low power (7uW) in small packaging (QFN). Voltage 1.2 and 3.3V.
config PHY_ROCKCHIP_USBDP tristate "Rockchip USBDP COMBO PHY Driver" depends on ARCH_ROCKCHIP select PHY help Enable this to support the Rockchip USB3.0/DP combo PHY with Samsung IP block. config PHY_ROCKCHIP_TYPEC bool "Rockchip TYPEC PHY Driver" 1 change: 1 addition & 0 deletions ...