Hey folks, Here is the pinout diagram for the Altera USB-Blaster JTAG cable as well as the USB box IDC socket.
Configuration Devices including: EPC1, EPC4 etc.Other Features ∙High download speed: FT245+CPLD+244, close to the original ALTERA USB Blaster.∙Download speed 1-3 times faster than other schemes, such as 68013 or C8051F.Connects to PC ∙Computer connection via USB 2.0 interface.
The PL-USB2-BLASTER belongs to Intel® FPGA Download Cable. This article will unlock its pinout, datasheet, block diagram, connection and more details about PL-USB2-BLASTER. Understanding and utilizing USB Blaster and JTAG to configure Intel FPGAs ...
This is firmware for STM32F103C8T6 microcontrollers implementing the Altera USB blaster protocol. It has been used with OpenOCD using stock USB Blaster configuration files. Pay attention to JTAG voltage levels, e.g. a 3.3V STM32 board can only be used with 3.3V targets. ...
Pinout Default TCK/DCLK pin is GP11 (blaster.c) Other data pins for simplicity are mapped sequentially relative to TCK/DCLK GPIO | I/O | name | JTAG | AS | PS ---+---+---+---+---+--- 11 | O | TCK_DCLK | TCK | DCLK | DCLK 12 | O | TMS_nCONFIG | TMS | nCONFIG...
and aStemma QT connectorthat lets you plug & play anyStemma QTor Qwiic devices, sensors and displays.This revision is completely back-compatible for board size, mounting holes and pinouts(the additional 3V/GND pins are where previously there were none and do not change the pinout, they can ...