待解决 悬赏分:1 - 离问题结束还有 This bit also causes the USART to issue an interrupt (Irpt_TFTLI) to the CPU when the TFTLIE bit in the IER register is set to 1 to enable the relevant interrupt and when the TFTL field in the FCR register is set to the value 0.问题补充:匿名 ...