Versal ACAP DDRMC - No Clock and Unconstrained Internal Endpoints with Non-Clock Sequential Cell Methodology Warnings when Using Internal HSM1 Reference Clock for DDRMC Description Version Found: Vivado 2022.2Version Resolved: See (Xilinx Answer 75764)When using the internal HSM1 reference clock for th...
(Check Timing >unconstrained_internal_endpoints>Unconstrained Pins for Maximum delay due to constraint clock) The reported logic is generated and constrained by the UltraScale FPGAs Transceiver Wizard. How should I address this? Solution This occurs because the driving clock (txoutclkpcs_out) is ga...