as unconstrained input port paths There are no unconstrained clocks reported. It seems the part between the ports clk1... and the pll input is missing, although the documentation says 'you do not have to generate the base clock on the input clock pin of the pll' ...
很明显,这是因为没有对输入port en进行必要的时序约束;而DC通过分析RTL得到了en与endpoint overflow_reg之间是存在时序关系的,但是由于并没有对应的时序约束,所以这条timing path是unconstrained.因此,解决方案是手动添加输入port en与clock 之间的时序约束关系,使用set_input_delay对en的setup和hold time进行时序约束;...
It write me, that the page not found and i solve now the same problem unconstrained ports, Input / Output port paths . Thank you very much. Jan --- Quote End --- Hi Jan, I do not know if these are the same tutorials I originally mentioned and I hope the...
[ find port [list $my_clock_pin] ] #if { $find_clock != [list] } { # set clk_name $my_clock_pin # create_clock -period $my_period $clk_name #} else { # set clk_name vclk # create_clock -period $my_period -name $clk_name #} #set_input_delay $my_input_delay_ns -...
Are you sure about your set_false_path command which cuts all the paths between the PLL input & output clock? For set_output_delay you can use ADDR [*], etc to be more comfort :):) What is your FPGA part & Quartus version? Translate 0 Kudos Copy link Reply Altera_Forum Hon...
The only major exception is for source-synchronous outputs, where the -clock should be the name of a create_generated_clock that is applied to the port driving out the clock. --- Quote End --- In my setup I want to constraint interface to sdram, so the "major exception" seems...
as unconstrained input port paths There are no unconstrained clocks reported. It seems the part between the ports clk1... and the pll input is missing, although the documentation says 'you do not have to generate the base clock on the input clock pin of ...
as unconstrained input port paths There are no unconstrained clocks reported. It seems the part between the ports clk1... and the pll input is missing, although the documentation says 'you do not have to generate the base clock on the input clock pin of the pll' in th...
as unconstrained input port paths There are no unconstrained clocks reported. It seems the part between the ports clk1... and the pll input is missing, although the documentation says 'you do not have to generate the base clock on the input clock pin of the...
as unconstrained input port paths There are no unconstrained clocks reported. It seems the part between the ports clk1... and the pll input is missing, although the documentation says 'you do not have to generate the base clock on the input clock pin of the...