集成手册ultra3000数字伺服驱动器编号2098-dsd n.pdf,Important User Information Because of the variety of uses for the products described in this publication, those responsible for the application and use of this control equipment must satisfy themselves th
8 Drive Enable input must be opened before main power is removed and auxiliary power is present, or a drive fault will occur. A delay of at least 1.0 second must be observed before attempting to enable the drive after main power is restored. 9 Cable shield clamp must be used in order ...
. . . . 173 Typical current consumption in Run mode with internal SMPS, with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 174 Typical current consumption in Run and Low-power run modes, with different codes running ...
STM32L412xx peripherals interconnect matrix (continued) Interconnect source Interconnect destination Interconnect action TIM15/TIM16 COMPx ADCx RTC IRTIM TIM1 TIM2 LPTIMERx TIM1 TIM16 LPTIMERx All clocks sources (internal TIM2 and external) TIM15, 16 CSS CPU (hard fault) RAM (parity error) ...
If the fault is hardware related, the problem could be any one of the components in the I/O path as depicted in Figure 3-1. For example, the defective component could be an FC/S card, FC/OM, or cable on the hosts for either node; or an FC/OM, the controller or I/O interface...
ANeg Complete Remote Fault Aneg. Ability Link Status Jabber Detect • 1 = Auto-Negotiate process completed. Reg. 4, 5, 6 are valid after this bit is set. • 0 = Auto-negotiate process not completed. • 1 = Remote fault condition detected. • 0 = No remote fault. This bit ...
Refer to Table 6.4 for I/O configuration. Internal Connections J3-20 J3-21 Function Drive Mode Select Integrator Inhibit Follower Enable Forward Enable Reverse Enable Operation Mode Override Table 6.4: INPUT1, INPUT2, INPUT3, INPUT4 and FAULT RESET Functions Description Active1 state configures ...
DIAG_ALRT Register Field Descriptions Type Reset Description R/W 0h When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Flag bit reset to the idle state when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and...
0010 Falling-edge Trigger FAULT-DUMP All Rising-edge No effect 0011 As per GPI-CH-SEL Falling-edge Rising-edge IOUT power-down IOUT power-up 0100 As per GPI-CH-SEL Falling-edge VOUT power-down. Pulldown resistor as per the VOUT-PDN-X setting Rising-edge VOUT power-up 0101 Falling-...
(5x5) • Up to 26 fast I/Os, most 5 V-tolerant • RTC with HW calendar, alarms and calibration • Up to 3 capacitive sensing channels • 11x timers: 1x 16-bit advanced motor-control, 1x 32-bit and 2x 16-bit general purpose, 2x 16- bit basic, 2x low-power 16-bit ...