The logic side contains a full-bridge driver, running at 2MHz, and is AC-coupled to a single transformer primary. A series DC blocking capacitor prevents trans- former saturation due to driver duty cycle imbalance. The transformer scales the primary voltage, and is rectified by a full-wave ...
potentiometer does not exceed 52.3kΩ.The value of RFFSDLY determines tPGDELAY according to the following equations: tPGDELAY ≈ 2.69ns / kΩ • RFFSDLY + 30ns tPGSG ≈ 20ns The SG pin must be connected to the secondary side MOSFET through a gate drive transformer as shown in Figure...