Check the following in your layout: 1. Large switched currents flow in the power switch, catch diode, and input capacitor. The loop formed by these components should be as small as possible. A ground plane is recommended to minimize ground impedance. 2. Connect the (+) terminal of the ...
following test standards: EN 61000-4-3 Radiated, radio-frequency, electromagnetic field immunity EN 61000-4-8 Power frequency magnetic field immunity EN 61000-4-9 Pulsed magnetic field immunity Tests were performed using an unshielded test card de- signed per the data sheet PCB layout ...
Check the following in your layout: 1. The power traces consisting of the PGND trace, the SW trace, the PVIN trace, the VIN and GNDA traces, should be kept short direct and wide. 2. Does each of the VFBx pins connect directly to the respective feedback resistors? The resistive ...
Check the following in your layout: 1. The power traces consisting of the PGND trace, the SW trace, the PVIN trace, the VIN and GNDA traces, should be kept short direct and wide. 2. Does each of the VFBx pins connect directly to the respective feedback resistors? The resistive ...
See the INPUT_0.IN_MODE bit field. The 8A34044 has the option to lock to the rising or falling edge of the input clock signal by selecting the inverted input path to the divider. When programmed as dual single-ended as shown in Figure 6, two independent inputs are provided to the 8...
Contact the local office or field support for the latest available information. TABLE 14. AVAILABLE DESIGN ASSISTANCE MATERIALS ITEM 1 DESCRIPTION SMBus/PMBus/I2C communication tool with the PowerNavigator GUI. 2 Evaluation board schematics in OrCAD format and layout in Allegro format. See Ordering ...
If this drain is too high, R2 can be increased to 41.2k, reducing divider current to 30µA. This introduces an addi- tional uncorrectable error to the constant voltage float mode of about ±0.5% as calculated by: VBAT Error = ± 0.15µA(R1)(R2) 1.245(R1+ R2) ±0.15µA =...
(See Applica- tions Information—Layout Considerations.) SW (Pin 2): The switch pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on-time. Inductor current drives the switch pin negative during switch off-time. Negative volt...
Check the following in your layout: 1. TheSchottkydiodeshouldbecloselyconnectedbetween the output capacitor and the drain of the external MOSFET. 2. The input decoupling capacitor (0.1µF) should be con- nected closely between VIN and GND. 3. The trace from SW to the switch point should...
The POR pin is a common drain output and requires a pull- up resistor. A 100k resistor is used for adequate speed. Figure 3 shows the complete schematic for this design example. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ...