module top; class cls1; typedef bit bool_t; endclass class cls2#(cls1::bool_t param); endclass cls2#(1) mycls; endmodule Output: %Error: Internal Error: top.sv:7:24: ../V3AstNodeDType.h:1191: Typedef not linked : ... note: In instance 'top' 7 | class cls2#(cls1#()...
The name of the parser: verilog.c The command line you used to run ctags: $ ctags --options=NONE foo.sv The content of input file: foo.sv typedef bit[31:0] int32_t; module mod( input bit clk, input int32_t a ); endmodule The tags output ...
systemverilog class forward declaration typedef in sv class instantiation before the class declaration typedef provides a forward declaration of the class