While sending data from FPGA to ADRV, the first stage is the transport layer that is implemented in tx_adrv9009_tpl_core (which contains JESD204 Transport Layer for DACs) in the default project provided by the AD. JESD204 Transport Layer for DACs IP has a 128 Bit Data port but ADRV...
I have an ADRV9009 and ZC706. Both of which send and receive data using jesd204b. While sending data from FPGA to ADRV, the first stage is the transport layer that is implemented intx_adrv9009_tpl_core(which containsJESD204 Transport Layer for DACs) in the default project provided by th...