In a multi-level logic gate circuit, the inputs are connected to intermediate logic gates, and the output is obtained by combining the outputs of these intermediate gates. This type of circuit can implement more complex logic functions compared to a two-level circuit, but it is more...
System level performance evaluation of three-dimensional integrated circuit power dissipationBased on a stochastic wire length distributed model, the reduction in the length of interconnects and gate pitch for three-dimensional (3D)... L Qian,Z Zhu,Y Yang - IEEE International Conference on Asic 被...
A two stage gate drive circuit (10) for controlling a power transistor (12) has been provided. The drive circuit includes a first stage (14) coupled to a first supply voltage terminal for providing a high current drive signal to the power transistor for quickly switching on the power ...
A drive circuit for an Electroluminesent display panel is disclosed in which a ground line is divided into two line, one of which is provided for a signal input stage and the other of which is provided for a signal output stage. The signal output stage includes two level- shift circuits,...
In this paper the comparative results of two layered and three layered coreless Printed Circuit Board (PCB) step down 2:1 power transformers operating in MHz frequency were addressed. The two different step down transformers approximately having same self inductances, one in two layer and the othe...
The divider circuit has a conventional first (10) and second (20) source load circuit, connected to each others source and grid of the respective first (11) and second (21) MESFETs, operating in a depletion mode. Interposed between these connections are the two switching circuits and one ...
Example of circuits synthesis show power reduction possibilities during design of two-level logic circuits based on information about primary input vector changes – a new circuit activity measure. 展开 DOI: 10.1007/11556930_47 被引量: 8 年份: 2005 ...
The PWM Generator (Three-phase, Two-level) block controls switching behavior for a three-phase, two-level power converter. The block: Calculates on- and off-gating times based on the block inputs: Three sinusoidal reference voltages, one per phase A DC-link voltage Uses the gating times ...
of the clock tree is coupled to receive the control signal for collectively conditionally gating the plurality of clock, and is also configured to individually conditionally gate at least some of the plurality of clocks responsive to activity in the respective subcircuits of the execution circuit. A...
In a level shift circuit including cascaded first and second CMOS inverters, the first CMOS inverter is powered by a first power supply voltage and a second power supply voltage lower than the first power supply voltage. Also, the second CMOS inverter is powered by the first power supply volta...