1 CPP 57nmMInimun metal pitch 40nmFin 最小 pitch 30nmSRAM area 0.027um2STD height 240nm可以看到9020的確有N7特徵,但在poly gate pitch做的比TSMC 還大另外從SRAM area 9020也比TSMC N7大,除了CPP差異有貢獻,9020的SRAM height 是250 nm ( 一組完整NPPN line的pitch),也比N7大SRAM面積是pull up/ ...
As devices scale down parasitic resistance and capacitance become a problem. Contacted Poly Pitch (CPP) determine standard cell widths (see figure 1) and is made up of Lg, Contact Width (Wc) and Spacer Thickness (Tsp), CPP = Lg + Wc + 2Tsp. Reducing Wc increases parasitic resistance unle...
People forgetting N7 used optical only is also irksome to me as well. IMO this fallacy also devalues how well targeted N7 was. Right at the limits of SALELE with the option to insert limited EUV to derisk N5. Tanj said: 10nm may have had weird pitch gearing. Intel 4 has lovely...